Silicon Materials and Devices R&D

NREL has world-leading research capabilities and expertise in silicon (Si) materials and devices, especially for photovoltaic (PV) cell applications.

2024 Workshop on Crystalline Silicon Solar Cells and Modules

July 28–31, 2024
Breckenridge, Colorado

Our Expertise

We have expertise in:

  • n-type monocrystalline-Si cells and the processes that enable them:
    • State-of-the-art deep B emitters
    • Surface passivation for B-doped and P-doped surfaces and wafers (atomic layer deposition of Al2O3, PECVD of SiNx, and SiO2 by thermal, chemical, and UV-ozone treatments)
    • n-PERT cells
    • Front B emitter + back-passivated tunneling contact cells
    • >22% all poly-Si/SiO2 passivated tunneling contact cells
    • Low-cost patterned doping techniques (masking, ion implantation, etching)
  • Thin-film Si: amorphous-Si:H, nanocrystalline-Si:H, epitaxial Si on seed templates
  • Amorphous-Si:H heterojunction cells
  • "Black" Si and porous Si processes for PV applications
  • Passivated tunneling contacts based on thin tunneling SiO2 with polycrystalline-Si and transparent conducting oxide layers
  • Passivated contacts based on nano-scale dielectric pin holes
  • Czochralski (Cz) Si crystal growth
  • Tabula Rasa process to mitigate bulk degradation in n-Cz Si due to oxygen precipitation
  • Tandems with Si bottom cell by direct III-V growth on Si, by transparent conducting oxide-mediated wafer bonding, and by mechanical stacking of III-V and Si cells
  • Novel conductive and transparent adhesives for solar cells and other device applications
  • In-depth, atomic-level studies of metallic contact paste firing  
  • Defects in mono- and multicrystalline cells
  • Atomic-level studies of lifetime degradation in n- and p-Cz wafers.

Research Areas

We are studying defects that are produced during growth and processing of n-type and p-type Cz and novel silicon (kerfless). The goal is to mitigate the deleterious impact of these defects to produce cells that have bulk carrier lifetimes exceeding 4 milliseconds (n-Cz) after all cell process steps. We are continuing to improve and understand our Tabula Rasa process for PV n-Cz wafers that suppresses oxygen precipitates, which getter impurity metals, form deep-level recombination sites during high-temperature processing steps, and lower lifetimes in the wafer. We are also studying light and temperature induced degradation mechanisms in p-type Cz wafers.
We are developing poly-Si/SiO2 passivated contact cells in both the front/back and interdigitated back-contact architectures that exhibit high performance—that is, open-circuit voltages greater than 700 mV. Our research focuses on the physics and engineering of passivated contact structures; this involves process development, density functional theory, and analytical microscopy studies. We work on interfaces that probe passivation, morphology, stability, and transport mechanisms. In the area of dopant patterning, we are pursuing plasma immersion ion implantation and other novel techniques such as selective area surface treatments and the use of nanoparticles.
Our goal is to develop a passivated contact cell that has a conversion efficiency above 23% at a cost consistent with the levelized cost of energy goals set within the Department of Energy's SunShot Initiative. Our approach is to draw from the advances in the bulk Cz Si and contact work described above, which will include implementing the Tabula Rasa process, passivated contact formation, patterned doping, and other innovations.

The interdigitated back-contact architecture holds the top three world records for cell efficiency, but the front/back architecture is likely the dominant cell structure for the near future. Our research seeks to reduce the cost of passivated contact cells while maintaining high efficiencies by using innovations in wafer lifetime preservation, low-recombination contacts, and low-cost metallization strategies.

Tools and Capabilities

Our tools and capabilities available for R&D in silicon materials and devices include:

  • A 20,000-ft2 cleanroom that houses 156-mm × 156-mm wafer-compatible tools, including an automated wet-process station and diffusion furnace. This facility allows reproducible processing of high-efficiency cells and collaboration with industry partners and other research laboratories.

  • Silicon cluster tool for large-area (156-mm × 156-mm) samples. This tool comprises eight process chambers for plasma-enhanced chemical vapor deposition of amorphous-Si-based intrinsic, doped, alloyed thin films, Si nitride, and sputtering of transparent conducting oxides.

  • Clean diffusion/oxidation processes for Si wafers that preserve multiple milliseconds lifetime; wet chemistries in the cleanroom that enable efficient Si cells

  • Czochralski puller for Si feedstock testing, with a maximum load of 5 kilograms

  • Cell and materials testing techniques, including current-voltage and quantum efficiency, Sinton lifetime, Suns-Voc, photoluminescence, electroluminescence, secondary ion mass spectrometry, electron beam induced current imaging, transmission electron microscopy, X-ray diffraction, Rutherford back scattering, lock-in thermography, photothermal deflection spectroscopy and constant photocurrent absorption, Raman and photoluminescence mapping, conductivity and activation energy, transient capacitance and capacitance-voltage, ellipsometry, fast-reflection and transmission measurements of optical properties, and method-of-four-coefficients (Hall, conductivity, Seebeck, Nernst)

  • Analytical microscopy and theory, which allows us to use high-resolution transmission electron microscopy, time-of-flight secondary-ion mass spectrometry, electron energy-loss spectroscopy, X-ray photoelectron spectroscopy, Auger electron spectroscopy, and other techniques as well as state-of-the-art density functional theory simulations of interfaces, contacts, and new materials

  • Inkjet printing of metallic, nanoparticle, and dopant inks, with express evaluation by X-ray fluorescence and X-ray diffraction

  • Defect visualization etching and mapping in multi- and mono-Si cells, express texture evaluation, and thermal processing in clean optical and diffusion furnaces.